Rajashekar Reddy Theegala
Worked on TSMC-7nm,16nm,28nm,40nm,150nm, INTL-10nm and GF-16nm. Macro count range from 12 to 857 Place and route using ICC2, FCCompiler, ICCompiler... | Hyderabad, Telangana, India
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Rajashekar Reddy Theegala’s Emails rt****@am****.com
Rajashekar Reddy Theegala’s Phone Numbers No phone number available.
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Rajashekar Reddy Theegala’s Location Hyderabad, Telangana, India
Rajashekar Reddy Theegala’s Expertise Worked on TSMC-7nm,16nm,28nm,40nm,150nm, INTL-10nm and GF-16nm. Macro count range from 12 to 857 Place and route using ICC2, FCCompiler, ICCompiler and Magma Timing signoff using Primetime Parasitic extraction using StarRC Physical verification (Calibre) Power Analysis (IR) using Redhawk EM using Redhawk
Rajashekar Reddy Theegala’s Current Industry Amd
Rajashekar
Reddy Theegala’s Prior Industry
Einfochips
|
Intel
|
Mediatek
|
Amd
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Work Experience
Amd
Asic Physical Design Engineer
Fri Oct 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time) — Present
Intel
Asic Physical Design Engineer
Fri Feb 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Oct 01 2021 00:00:00 GMT+0000 (Coordinated Universal Time)
Mediatek
Senior Physical Design Engineer
Thu Oct 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Fri Feb 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time)
Intel
Senior Physical Design Engineer
Sun Mar 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time) — Tue Sep 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)
Einfochips
Physical Design Engineer
Sun Jan 01 2012 00:00:00 GMT+0000 (Coordinated Universal Time) — Sun Feb 01 2015 00:00:00 GMT+0000 (Coordinated Universal Time)Skills
Languages
Rajashekar Reddy Theegala Email Addresses
FAQ About Rajashekar Reddy Theegala
-
Rajashekar Reddy Theegala is located at
Hyderabad, Telangana, India -
Rajashekar Reddy Theegala is a
Worked on TSMC-7nm,16nm,28nm,40nm,150nm, INTL-10nm and GF-16nm. Macro count range from 12 to 857 Place and route using ICC2, FCCompiler, ICCompiler and Magma Timing signoff using Primetime Parasitic extraction using StarRC Physical verification (Calibre) Power Analysis (IR) using Redhawk EM using Redhawk Amd -
Rajashekar Reddy Theegala currently works in the
Amd -
Rajashekar Reddy Theegala specializes in
Worked on TSMC-7nm,16nm,28nm,40nm,150nm, INTL-10nm and GF-16nm. Macro count range from 12 to 857 Place and route using ICC2, FCCompiler, ICCompiler and Magma Timing signoff using Primetime Parasitic extraction using StarRC Physical verification (Calibre) Power Analysis (IR) using Redhawk EM using Redhawk -
Rajashekar Reddy Theegala speaks the following languages:
No languages available. -
Rajashekar Reddy Theegala has prior experience in the following industries:
Intel , Mediatek , Intel , Einfochips -
Rajashekar Reddy Theegala has the following professional experience:
Amd , Intel , Mediatek , Intel , Einfochips . -
You can view Rajashekar Reddy Theegala’s
LinkedIn profile at LinkedIn URL. -
Rajashekar Reddy Theegala’s work email addresses are
[email protected] . -
Rajashekar Reddy Theegala works at
Amd
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